MB15F02 Datasheet, PDF (7/24 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F02
s FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO: Output frequency of external voltage controlled ocillator (VCO)
M: Preset divide ratio of dual modulus prescaler (16 or 32 for IF-PLL, 64 or 128 for RF-PLL)
N: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
fOSC: Reference oscillation frequency
R: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF–PLL
sections, programmable reference dividers of IF/RF PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On rising edge of clock, one bit of serial data is transferred into the shift register. When load enable signal is high,
the data stored in the shift register is transferred to one of latch of them depending upon the control bit data setting.
Table1. Control Bit
Control bit
CN1
CN2
L
L
H
L
L
H
H
H
Destination of serial data
The programmable reference counter for the IF-PLL.
The programmable reference counter for the RF-PLL.
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
Shift Register Configuration
Programmable Reference Counter
LS
Data
MS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
CC T T R R R R R R R R R R R R R R
N N 1 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14
12
CNT1, 2 : Control bit
R1 to R14 : Divide ratio setting bits for the programmable reference counter (5 to 16,383)
T1, 2
: Test purpose bit
NOTE: Start data input with MSB first.
[Table. 1]
[Table. 2]
[Table. 3]
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