MB15F02 Datasheet, PDF (11/24 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

s PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
LD
(FC bit = High)
DoIF/RF
Z
tWU
H
(FC bit = Low)
DoIF/RF
Z
tWL
L
MB15F02
LD Output Logic Table
IF–PLL section
RF–PLL section
LD output
Locking state / Power saving state Locking state / Power saving state
H
Locking state / Power saving state Unlocking state
L
Unlocking state
Unlocking state
Locking state / Power saving state
L
Unlocking state
L
Note: • Phase error detection range = −2π to +2π
• Pulses on DoIF/RF signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCin input frequency as follows.
tWU > 8/fosc: i.e. tWU > 625ns when foscin = 12.8 MHz
tWL < 16/fosc: i.e. tWL < 1250ns when foscin = 12.8 MHz
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