MB1511 Datasheet, PDF (7/15 Pages) Fujitsu Component Limited. – Serial Input PLL Frequency Synthesizer

MB1511
(2) Programmable Divider
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable
counter. Serial 19-bit data format is shown following page.
Control bit
LSB
MSB
C S S S S S S S S S S S S S S SSS S
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Divide ratio of swallow
counter setting bit
Divide ratio of programmable
counter setting bit
• 7-bit Swallow Counter Divide Ratio
Divide Ratio S S S S S S S
A
7654321
0
0000000
1
0000001
• 11-bit Programmable Counter Divide Ratio
Divide Ratio S S S S S S S S S S S
N
18 17 16 15 14 13 12 11 10 9 8
16
00000010001
17
00000010001
127
1111111
Note: Divide ratio: 0 to 127
2047 1 1 1 1 1 1 1 1 1 1 1
Notes:
Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
3. Serial Data Input Timing
t 1~t 5 ≤ 1 µs
Data S18 = MSB S17
* (SW)
Clock
(S14)
LE
S10
S9
(S8)
(S7)
S1 = LSB
C : CONTROL BIT
(S1)
(C : CONTROL BIT)
t1
t2
t3
t4
t5
Notes: Paranthesis data is used for setting divide ratio of programmable reference divider.
On rising edge of clock shifts one bit of data in the shift register.
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