MB1511 Datasheet, PDF (5/15 Pages) Fujitsu Component Limited. – Serial Input PLL Frequency Synthesizer

MB1511
s FUNCTIONAL DESCRIPTIONS
1. Pulse Swallow Function
The divide ratio is set using the following equation.
fVCO = [(M × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
M : Preset modulus of external dual modulus prescaler (64 or 128)
N : Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Output frequency of the external reference frequency oscillator
R : Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
2. Serial Data Input
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-
bit programmable reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high
level or open, stored data is transferred into latch depending upon the control bit.
Control data "H" data is transferred into 15-bit latch.
Control data "L" data is transferred into 18-bit latch.
5