MB1511 Datasheet, PDF (6/15 Pages) Fujitsu Component Limited. – Serial Input PLL Frequency Synthesizer

MB1511
(1) Programmable Reference Divider
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial
16-bit data format is shown below.
Control bit
LSB
Divide ratio of prescaler setting bit
MSB
CSSSSSSSSSSSSSSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 W
Divide ratio of programmable reference counter setting bit
• 14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide Ratio S S S S S S S S S S S S S S
R
14 13 12 11 10 9 8 7 6 5 4 3 2 1
8
00000000001000
9
00000000001001
16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler.
SW = H: 64/65
SW = L: 128/129
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
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