MB85RC64 Datasheet, PDF (6/20 Pages) Fujitsu Component Limited. – Memory FRAM 64 K (8 K x 8) Bit I2C

MB85RC64
■ DEVICE ADDRESS WORD (Slave address)
Following the start condition, the bus master sends the 8bits device address word (Slave address) to start
I²C communication. The device address word (8bits) consists of a device Type code (4bits), device address
code (3bits), and a read/write code (1bit).
• Device Type Code (4bits)
The upper 4 bits of the device address word are a device type code that identifies the device type, and are
fixed at “1010” for the MB85RC64.
• Device Address Code (3bits)
Following the device type code, the 3 bits of the device address code are input in order of A2, A1, and A0.
Each MB85RC64 is given a unique 3bits code on the device address pin (external hardware pin A2, A1, and
A0). When the device address code is received by the slave device, the slave only responds if the hardware
device address of which is equal to its unique 3bits code.
• Read/Write Code (1bit)
The 8th bit of the device address word is the R/W (read/write) code. When the R/W code is “0”, a write
operation is enabled, and the R/W code is “1”, a read operation is enabled for the MB85RC64.
It turns to a stand-by state if the device code is not “1010” or device address code does not equal to pins
A2, A1, and A0.
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DS05–13109–3E