MB85RC64 Datasheet, PDF (5/20 Pages) Fujitsu Component Limited. – Memory FRAM 64 K (8 K x 8) Bit I2C

MB85RC64
■ ACKNOWLEDGE (ACK)
In the I²C bus, serial data including address or memory information is sent in units of 8 bits. The acknowledge
signal indicates that every each 8 bits of the data is successfully sent and received. The information receiver
side usually outputs “L” every time on the 9th SCL clock after each 8 bits are successfully transmitted. On
the transmitter side, the bus is temporarily released to Hi-Z every time on this 9th clock to allow the acknowl-
edge signal to be received and checked. During this Hi-Z-released period, the receiver side pulls the SDA
line down to indicate “L” that the previous 8bits communication is successfully received.
If the information receiver side detects Stop condition before driving the acknowledge “L”, the read operation
ends and the I²C bus enters the standby state. If Stop condition is not sent, nor does the transmitter detect
the acknowledge “L”, the bus remains in the released state “H” without doing anything.
• Acknowledge timing overview diagram
SCL
1
2
3
8
9
SDA
Start
The transmitter side should always release SDA on the
9th bit. At this time, the receiver side outputs a pull-down
to indicate a successful byte transfer (ACK response).
ACK
DS05–13109–3E
5