MB85RC64 Datasheet, PDF (3/20 Pages) Fujitsu Component Limited. – Memory FRAM 64 K (8 K x 8) Bit I2C

■ BLOCK DIAGRAM
SDA
Serial/Parallel Converter
SCL
WP
A0, A1, A2
MB85RC64
FRAM Array
8,192 × 8
Column Decoder/Sense Amp/
Write Amp
■ I²C (Inter-Integrated Circuit)
The MB85RC64 has the two-wire serial interface; the I²C bus,and operates as a slave device.
The I²C bus defines communication roles of “master” and “slave” devices, with the master side holding the
authority to initiate control. Furthermore, a I²C bus connection is possible where a single master device is
connected to multiple slave devices in a party-line configuration. In this case, it is necessary to assign a
unique device address to the slave device.
• I²C Interface System Configuration Example
SCL
SDA
VDD
Pull-up
Resistors
I²C Bus
Master
I²C Bus
MB85RC64
A2 A1 A0
000
Device address
I²C Bus
MB85RC64
A2 A1 A0
001
I²C Bus
MB85RC64
A2 A1 A0
010
...
DS05–13109–3E
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