MB3782_1 Datasheet, PDF (6/27 Pages) Fujitsu Component Limited. – ASSP Power Supplies BIPOLAR Switching Regulator Controller

MB3782
s SETTING THE TIME CONSTANT FOR THE TIMER-LATCH TYPE SHORT PREVENTION
CIRCUIT
Figure 1 shows the configuration of the protection latch circuit.
The output lines from the error amps are each connected to the inverting input lines of the short protection
comparator, which constantly compares them with the reference voltage of approximately 2.1 V connected to
the non-inverting input.
When load conditions in the switching regulator are stabilized, there is no variation in the output from the error
amps, and therefore the short prevention controls are held in equilibrium. In this situation, voltage at the SCP
pin (pin 14) is held at approximately 50 mV.
When load conditions change rapidly, as in the case of a load short, high potential signal (greater than 2.1V)
from the error amps is input to the inverting signal input of the short protection comparator, and the short protection
comparator outputs a “low” level signal. The transistor Q1 is consequently switched off, so that short protection
capacitor CPE externally connected to the SCP pin voltage is then charged according to the following formulas.
VPE = 50 mV + tPE × 10^–6/CPE
0.65 = 50 mV + tPE × 10^–6/CPE
CPE = tPE/0.6 (µF)
When the short protection capacitor is charged to a level of approximately 0.65 V, the SR latch is set and the
low input voltage fault prevention circuit is enabled, turning the output drive transistor off. At the same time, the
dead time is set to 100% and the SCP pin (pin 14) is held “low.” This closes the S-R latch input and then
discharges the capacitor CPE
2.50 V
1 µA
S.C.P.Comp.
Error Amp.1 –
14
Out
PWM
Error Amp.2 –
Error Amp.3 –
CPE ^{S R}
Comp.
U.V.L.O.
+
Q1
Q3
Latch
2.1 V
Figure 1 Protection Latch Circuit
6