MB40C348 Datasheet, PDF (5/19 Pages) Fujitsu Component Limited. – 3 ch 8-bit 100 MSPS A/D Converter

s BLOCK DIAGRAM
MB40C348
VESD VREFT VREFB AVDD DVDD
VRTM VRT VRB VRBM VR1 VR2 VR3
PCLP
RADIN
RVIN
RVCLP
R
R
× 1.9
VREF Amp. Block
OF
AMP + CLAMP + A/D
× 3 ch
A ch
8
8
8 bit A/D
Buffer
RDA0
∼ RDA7
B ch
8
8
8 bit A/D
Buffer
RDB0
∼ RDB7
Buffer
ADCLKA
PLL Block
Buffer
ADCLKB
CE
RESET _1/2
AVSS
2 bit (0 ∼ 3 CLK)
DVSS
CLK Delay
Delay
Buffer
DSYNC
6 bit (32 divide, 2CLK)
Buffer
DSYNCB
HSYNC
POL
(1 bit)
PD
CP
VCO
MUX
DIV
2 bit
(1 ∼ 1/8)
Buffer
Buffer
CLK
CLKB
HHOLD
Counter
(12 bit)
11 bit Shift
COUT
LPF EXPCLKB EXCLK
EXPCLK
Filter
PVSS PVDD CK DATA CS
5