MB40C348 Datasheet, PDF (10/19 Pages) Fujitsu Component Limited. – 3 ch 8-bit 100 MSPS A/D Converter

MB40C348
s SERIAL DATA SETTING (MSB Fast)
(Address)
(Data)
LSB
MSB
RES D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Function
1 1 0 0 0 0 0 0 0 0 1 0 Counter low ranking 8 bit
2 0 1 0 0 0 0 0 X X X X Counter high ranking 4 bit
1 1 0 0 0 0 0 0 0 1 0 CLK delay adjust*¹ : td = N/ (32 ×fCLK)
3 ^{1 1 0 0 0 0 0 0 0 1 0 HSYNC polarity : 0 = through, 1 = inversion}
1
1
0
0
0
0
0
0
0
1
0
A/D converter output : 0 = operation,
1 = high impedance
0 0 1 0 0 0 0 0 0 1 0 CLK output : 0 = on, 1 = “L”
0 0 1 0 0 0 0 0 0 1 0 CLKB output : 0 = on, 1 = “L”
0 0 1 0 0 0 0 0 0 1 0 DSYNC output : 0 = on, 1 = “L”
4 0 0 1 0 0 0 0 0 0 1 0 DSYNCB output : 0 = on, 1 = “L”
0 0 1 0 0 0 0 0 0 1 0 ADCLKA output : 0 = on, 1 = “L”
0 0 1 0 0 0 0 0 0 1 0 ADCLKB output : 0 = on, 1 = “L”
0 0 1 0 0 0 0 0 0 1 0 DSYNC delay*² : 0, 1, 2, 3
1 0 1 0 0 0 0 0 0 1 0 CLK change : 0 = VCO, 1 = External clock
1 0 1 0 0 0 0 0 0 1 0 External clock input : 0 = CMOS, 1 = PECL
1 0 1 0 0 0 0 0 0 1 0 Counter operation : 0 = on, 1 = off
5
1
0
1
0
0
0
0
0
0
1
0
Charge pump current*³ :
0.1 mA, 0.5 mA, 1 mA
1 0 1 0 0 0 0 0 0 1 0 VCO select : 0 = VCOL, 1 = VCOH
1 0 1 0 0 0 0 0 0 1 0 Divider setting*⁴ : 1, 1/2, 1/4, 1/8
*1 : Setting at 6bit, Resolution: 1/32 ×CLK, Setting range: 0 to 63/32 ×CLK
*2, *3, *4 : See under table
Setting
0 (0, 0)
1 (1, 0)
2 (0, 1)
DSYNC Delay*²
0 CLK
1 CLK
2 CLK
Charge pump current*³
0.1 mA
0.5 mA
1.0 mA
Divider setting*⁴
1/1
1/2
1/4
Example: input at 16 bit
MSB
DATA input
The invalid data
DATA
3 (1, 1)
3 CLK

1/8
LSB
Address
CS input
(5 bit)
(8 bit)
(3 bit)
10