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MB40C348 Datasheet, PDF (13/19 Pages) Fujitsu Component Limited. – 3 ch 8-bit 100 MSPS A/D Converter | |||
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MB40C348
⢠Demultiplex Output (in-phase) Mode (Timing Diagram 2)
VIHD
HSYNC input
VILD
VOHD
CLKB output
CLK output
VOLD
VOHD
DSYNC output
VOLD
VOHD
ADCLKA output
VOLD
VOHD
ADCLKB output
VOLD
tpd (HSYNC-CLK)
tpd (CLK-DSYNC)
tpd (CLK-ADCLK2)
ADIN input
N
N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9
tAD
VOHD
DA0 to DA7 output X
X
VOLD
VOHD
DB0 to DB7 output X
X
VOLD
VOHD
OF output
X
X
VOLD
X
X
X
X
X
X
tpd (CLK-DATA2)
X
N
N+2
X
N+1
N+3
X
N
N+2
⢠ADIN input : Sampling at CLK rising (at CLKB falling)
⢠DA0 to DA7 : Output (after 6CLK + tpd(CLKâDATA2) from sampling) at CLK rising (at CLKB falling)
⢠DB0 to DB7 : Output (after 5CLK + tpd(CLKâDATA2) from sampling) at CLK rising (at CLKB falling)
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