MB90560 Datasheet, PDF (413/581 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

q Stop Bit
For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only
one that is always checked.
q Error Detection
• In mode 0, parity, overrun, and framing errors can be detected.
• In mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
q Parity 0
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide
parity can be specified using the PEN bit of the serial control register (SCR0/1). Even or odd
parity can also be specified using the P bit of the serial control register (SCR0/1). In operation
mode 1 (asynchronous, multiprocessor mode) and operation mode 2 (synchronous, normal
mode), parity cannot be used. Figure 13.7-2 shows both transmission and receive data when
parity is enabled.
SIN1
ST
SP
1011000
A parity error occurs
during reception with even parity.
(SCR1: P=0)
SOT1
ST
SP
1011001
Transmission with even parity
(SCR1: P=0)
SOT1
ST
SP
1011000
Data
ST : Start bit
SP : Stop bit
Note : Parity is disabled in operation modes 1 and 2.
Parity
Transmission with odd parity
(SCR1: P=1)
Figure 13.7-2 Transmission data when parity is enabled
MB90560 series
CHAPTER 13 UART 389