MB90560 Datasheet, PDF (280/581 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

11.4 16-Bit Reload Timer Registers
11.4.1 Timer control status register, upper part (TMCSR0, TMCSR1:
H)
Bits 11 to bit 7 of the timer control status registers (TMCSR0 and TMCSR1) are used to
select the operating mode of the 16-bit reload timer and set the operating conditions.
This section describes bit 7: the MOD0 bit.
s Timer control status register, upper part (TMCSR0, TMCSR1: H)
Address
TMCSR0
000083H
TMCSR1
000087 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6
bit0
Initial value
CSL1 CSL0 MOD2 MOD1 MOD0 ^{TMSCR L} XXXX00000B
R/W R/W R/W R/W R/W
MOD2 MOD1 MOD0
000
001
010
011
1X0
1X1
Operating mode selection bit
(Internal clock mode)
Input pin function
Valid edge and level
Trigger disabled
Rising edge
Trigger input
Falling edge
Both edges
Gate input
"L" level
"H" level
MOD2 MOD1 MOD0
X00
X01
X10
X11
Operating mode selection bit
(Event clock mode)
Input pin function
Valid edge
Event input
Rising edge
Falling edge
Both edges
CSL1 CSL0
Count clock selection bit
Function
Count clock
00
2¹ / (0.125 µS)
01
Internal clock mode
2³ / (0.5 µS)
R/W _Read/Write
10
Not used
X
Undefined
11
Event clock mode
Initial value
Machine cycle. Value in parentheres are for 16MHz machine clock
2 ⁵/ (2.0 µS)
External event input
Figure 11.4-2 Timer control status register, upper part (TMCSR0, TMCSR1: H)
256 CHAPTER 11 16-BIT RELOAD TIMER
MB90560 series