MB90560 Datasheet, PDF (403/581 Pages) Fujitsu Component Limited. – 16-BIT MICROCONTROLLER

q Synchronous Transfer Clock Division Ratios
A division ratio for synchronous baud rates is selected using the CS2 to CS0 bits of the mode
control register (SMR0/1) as listed in Table 13.6-2.
Table 13.6-2 Selection of synchronous baud rate division ratios
CS2 CS1 CS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
Division ratio for CLK
synchronization
16M
8M
4M
2M
1M
500K
Calculation formula
( φ ÷ div)/1
( φ ÷ div)/2
( φ ÷ div)/4
( φ ÷ div)/8
( φ ÷ div)/16
( φ ÷ div)/32
SCKI
( φ ÷ div)/1
( φ ÷ div)/2
( φ ÷ div)/4
( φ ÷ div)/8
( φ ÷ div)/16
( φ ÷ div)/32
The division ratio is calculated supposing that machine cycle φ = 16 MHz and div = 4.
q Asynchronous Transfer Clock Division Ratios
A division ratio for asynchronous baud rates is selected using the CS2 to CS0 bits of the mode
control register (SMR0/1) as listed in Table 13.6-3.
Table 13.6-3 Selection of synchronous baud rate division ratios
CS2 CS1 CS0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
Asynchronus (start-
stop synchronization)
76923
38461
19230
9615
500K
250K
Calculation formula
( φ ÷ div)/(8x13x2)
( φ ÷ div)/(8x13x4)
( φ ÷ div)/(8x13x8)
( φ ÷ div)/(8x13x16)
( φ ÷ div)/(8x2x2)
( φ ÷ div)/(8x13x4)
SCKI
( φ ÷ div)/(13x1)
( φ ÷ div)/(13x2)
( φ ÷ div)/(13x4)
( φ ÷ div)/(13x8)
( φ ÷ div)/2
( φ ÷ div)/4
The division ratio is calculated supposing that machine cycle φ = 16 MHz and div = 1.
MB90560 series
CHAPTER 13 UART 379