MB40C338 Datasheet, PDF (4/18 Pages) Fujitsu Component Limited. – 3 ch 8-bit 162 MSPS A/D Converter

MB40C338
(Continued)
Parameter Symbol
Description
99
EXPCLKB
Differential clock (negative-phase) input pin for A/D converter
Fix to “H” level when unused.
PECL level
100
EXPCLK
Differential clock (positive-phase) input pin for A/D converter
Fix to “L” level when unused.
8
PCLP
Clamp pulse input pin
4
CE
Power down at CE input “H” (internal pull-up resistor)
113
RREF
Internal current setting pin (Add 12 kΩ for AVSS)
103
DSYNC Delay sync signal output pin
102
DSYNCB Inverted delay sync signal output pin
95
CLK
94
CLKB
Clock output pin (See “s TIMING DIAGRAM”.)
97
ADCLKA
96
ADCLKB
83 to 90
61 to 68
39 to 46
RDA7 to RDA0
GDA7 to GDA0
BDA7 to BDA0
Digital output pin (Port A)
RDA7, GDA7, BDA7 : MSB
RDA0, GDA0, BDA0 : LSB
71 to 78
51 to 58
29 to 36
RDB7 to RDB0
GDB7 to GDB0
BDB7 to BDB0
Digital output pin (Port B)
RDB7, GDB7, BDB7 : MSB
RDB0, GDB0, BDB0 : LSB
101
COUT PLL counter output pin
115
LPF
External capacitor/resistor connection pin
117
HHOLD Phase detector operation is hold by input “H” level
118
HSYNC Horizontal sync signal input pin
7
VREF
Internal voltage output pin (Add 3.3µF for AVSS)
104
OF
Overflow output pin (“H” level output at overflow)
Note: The values in parentheses are standard.
4