MB86064 Datasheet, PDF (3/4 Pages) Fujitsu Component Limited. – Dual 14-bit 1GSa/s DAC

October 2004 Version 1.1
FME/MS/DAC80/FL/5085
MB86064 Dual 14-bit 1GSa/s DAC
Line 3 illustrates a conventional DAC
running at half rate.
Input Data
Unsigned binary data to each DAC core is
input via a dedicated parallel LVDS port. As
with the DAC core, data is latched on every
rising and falling edge of the clock in a
pseudo DDR mode. For synchronisation of
data generator(s) two LVDS clock outputs
and a Loop-Clock facility are provided.
dBFS
0
-6
Target high direct-IF
generating region
Frequency
Figure 2 Benefits of DAC core architecture to
Sinx/x response
Loop-Clock
Maintaining valid clock-to-data timing becomes increasingly difficult at higher clock rates, particularly
taking into account device-to-device variations. The MB86064 minimises potential problems through
its DDR data interface and by providing a loop-clock facility. The on-chip ‘loop’ consists of an LVDS
input connected to an LVDS output, through a programmable delay stage. This loop-through, and the
associated tracking from the data generating device, should be incorporated in the feedback loop of
a Delay-Locked Loop (DLL) or Phase-Locked Loop (PLL) clock generator, within the data generating
device. This enables the system to compensate for variations in input/output delays in both the data
generating device and the DAC.
Performance Enhancement Features
Each DAC core integrates a number of performance enhancing features. Performance levels now
reach the level sought after for next generation systems and high direct-IF architectures.
Serial Control Interface
A Fujitsu 4-wire serial interface is provided for configuration and control of the DAC. Programmed
data is stored in a number of read/writable registers.
Waveform Memory Module
The MB86064 incorporates a Waveform Memory Module featuring two 16k point on-chip waveform
memories. These allow the DAC cores to be driven with user programmed waveforms without the
need for external high speed, pattern generators.
Development Kit
A comprehensive Development Kit (DK),
DK86064, is available which comprises a
number of modules. A base motherboard
provides an interface to the DAC, Clock and
Data modules. Also included is a PC USB
Interface Lead & Control Software.
For further details, please refer to the
associated documentation.
Copyright © 2004 Fujitsu Microelectronics Europe GmbH
Production
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Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.