MB86064 Datasheet, PDF (2/4 Pages) Fujitsu Component Limited. – Dual 14-bit 1GSa/s DAC

October 2004 Version 1.1
FME/MS/DAC80/FL/5085
MB86064 Dual 14-bit 1GSa/s DAC
Functional Overview
The MB86064 is a high performance Dual 14-bit 1GSa/s DAC. In addition to two DAC cores the
device features a host of features designed to help both system integration and operation. A
functional block diagram is shown in Figure 1. Analog performance at high frequencies is enhanced
by novel current switch and switch driver designs which provide constant data-independent switching
delay, reducing jitter and distortion.
Control Interface
1.8V LVCMOS
RF Clock input
e.g. 500MHz
4-wire Serial Control Interface
÷
1, 2, 4, 8
÷
1, 2, 4, 8
Clock output 1
LVDS
Clock output 2
LVDS
Port A data input
14-bit LVDS
Loop clock input
LVDS
Loop clock output
LVDS
Port B data input
14-bit LVDS
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(16K Points)
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(16K Points)
Double-Edge
clocked
(1GSa/s)
DAC A
(14-bit)
Analog output A
DAC B
(14-bit)
Analog output B
EFBGA-120
Figure 1 MB86064 Functional Block Diagram
The device requires an input clock at half the DAC conversion rate as each DAC core is clocked on
both edges of the input clock. Each DAC core can be regarded as two interleaved DACs, each
running at half rate. The main reason for adopting this approach is that the switch driver inherently
includes a multiplex function through its two input ports. Compared to a conventional switch driver
this allows twice as long to acquire and convert, though because the two paths share current sources
they match exactly at low frequencies. A characteristic of this architecture is a suppressed image
appearing reflected about Fs(dac)/4 of Fclk-Fsig. Duty cycle error in the input clock will exacerbate
this image, but can be minimised by trimming the differential DC offset at the clock input pins.
The big advantage of this approach compared to a single DAC running at half the rate is much
reduced sinx/x roll off, which gives increased output power and better in-band flatness when
generating high output frequencies (e.g. 200MHz and above). This is illustrated in Figure 2 as line 1.
An alternative approach using a return-to-zero output stage has the same sinx/x roll off (and switch
driver speed) but 6dB lower output power and a large image at Fclk-Fout. See Line 2.
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Copyright © 2004 Fujitsu Microelectronics Europe GmbH
Disclaimer: The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.