MB85R1001 Datasheet, PDF (3/12 Pages) Fujitsu Component Limited. – 1 M Bit (128 K × 8)

MB85R1001
■ BLOCK DIAGRAM
A0
to ^·
·
·
Row Dec. Ferro Capacitor Cell
A16
intCE2
Column Dec.
CE2
WE
OE
CE1
intCEB
intCE2
intOE
intWE
intCE2
intCEB
S/A
I/O1 to I/O8
I/O8
· _to
·
I/O1
■ FUNCTION TRUTH TABLE
Operation Mode
CE1 CE2 WE OE
H
X
X
X
I/O1 to I/O8
Standby Pre-charge
X
L
X
X
High-Z
X
X
H
H
Read
Read
(Pseudo SRAM, OE control)
H
H
L
L
L
H
H
Dout
Write
H
L
H
L
Din
Write
(Pseudo SRAM, WE control)
L
H
H
Output Disable
L
H
H
H
High-Z
L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance
: Latch address at falling edge,
: Latch address at rising edge
Supply Current
Standby
(ISB)
Operation
(ICC)
3