MB39A115 Datasheet, PDF (27/42 Pages) Fujitsu Component Limited. – 5 ch DC/DC Converter IC with Synchronous Rectification

MB39A115
■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each threshold
voltage (VTH1, 2) of UVLO1 and UVLO2 (under voltage lockout protection circuit) , UVLO1 and UVLO2 are
released, and the operation of output drive circuit of each channel becomes possible.
When CTL is off, VR and VREF fall. When VREF decreases and UVLO1 and UVLO2 fall below each reset
voltage (VRST1, 2) , UVLO operates and output drive circuit of each channel is forcibly done the operation stop,
and makes the output an off state.
In the period until reaching to 2.0 V by VREF voltage after UVLO1 and UVLO2 are released by turning on CTL
(refer to a and b in “• Timing chart”) and the period until decreasing of VREF from 2.0 V after off CTL and
operating of UVLO1 and UVLO2 (refer to a’ and b’ in “• Timing chart”) , the bias voltage and the bias current in
IC do not reach a prescribed value because VREF which is the reference voltage does not reach 2.0 V, and
the speed of response of IC has decreased.
Moreover, when in this period IC does the input sudden charge or the load sudden charge or turning on and off
of CTL3 to CTL5, IC cannot conform and the output might overshoot. Therefore, impress the voltage to CTL
terminal by which the VREF voltage never stays in the above-mentioned period.
• CTL block equivalent circuit
SCP
UVLO2
UVLO1
H : at SCP
H : UVLO release
bias
H : UVLO release
ch.1 to ch.4
To output drive circuit
H : Possible to operate
L : Forced stop
CS1 to CS4
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
ch.5
To output drive circuit
H : Possible to operate
L : Forced stop
CS5
Error Amp reference To charge/discharge circuit
1.0 V/1.23 V H : Possible to charge
L : Forced discharge
VCC
5
VREF
Power
VR
ON/OFF
CTL
CTL
6
11
VREF
27