MB39A115 Datasheet, PDF (15/42 Pages) Fujitsu Component Limited. – 5 ch DC/DC Converter IC with Synchronous Rectification

MB39A115
■ FUNCTIONAL DESCRIPTION
1. DC/DC Converter Function
(1) Reference voltage block (VREF)
The reference voltage circuit uses the voltage supplied from the VCC terminal (pin 5) to generate a temperature
compensated stable voltage (2.0 V Typ) used as the reference voltage for the internal circuits of the IC. It is also
possible to supply the load current of up to 1 mA to external circuits as a reference voltage through the VREF
terminal (pin 11) .
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block generates the triangular wave oscillation waveform width with 0.4 V to
0.9 V by the timing resistor (RT ) connected to the RT terminal (pin 12) , and the timing capacitor (CT) connected
to the CT terminal (pin 13) . The triangular wave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1 to Error Amp5)
The error amplifier detects output voltage of the DC/DC converter and outputs PWM control signals. An arbitrary
loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to inverted input
terminal of the error amplifier, enabling stable phase compensation for the system.
You can prevent surge currents when the IC is turned on by connecting soft-start capacitors to the CS1 terminal
(pin 38) to CS5 terminal (pin 27) which are the noninverting input terminals of the error amplifier. The IC is started
up at constant soft-start time intervals independent of the output load of the DC-DC converter.
(4) PWM comparator block (PWM Comp.1 to PWM Comp.5)
The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on the
input/output voltage.
An external output transistor is turned on, during intervals when the error amplifier output voltage and DTC
voltage is higher than the triangular wave voltage.
(5) Output block (Drive1 to Drive5)
The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main
side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectification side of ch.1 and ch.5).
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