MB3829 Datasheet, PDF (18/24 Pages) Fujitsu Component Limited. – System Power Supply IC for Mobile Telephone

MB3829
DESCRIPTION OF OPERATION
(The numbers in the timing diagram correlate to the numbers (1) to (13) below.)
(1) When the REG1 output voltage (OUT1) is about 0.8 V (V_CCL), the reset signal is output.
(2) When OUT1 reaches a level higher than the detection voltage (V_SH), the power - on reset/hold time setup ca-
pacitor (C_TP) begins to charge. The V_SH value is 2.81 V.
(3) When the power - on reset/hold time setup pin (C_TP) voltage rises above the threshold level (Vth), the reset
clears (RESET pin voltage changes from L level to H level). The Vth value is about 1.9 V.
The power - on reset/hold time (t_PR) is expressed by the following equation.
Also, the watchdog timer monitoring time setup capacitor (C_TW) begins to charge.
t_PR [ms] » A x C_TP [mF]
A » 700
(4) When the watchdog timer monitoring time setup pin (C_TW) voltage reaches the Hi level (V_H), the C_TW changes
from the charged state to the discharged state. The V_H value is about the reference voltage of 1.24 V.
(5) When a clock pulse input is applied to the clock pin (CK) and then the next clock pulse input is applied (positive
edge trigger)
occurs.
to
the
CK
pin
during
a
C_TW
discharge,
switching
from
the
discharged
state
to
the
charged
state
(6) If a clock pulse input is not delivered to the clock pin (CK) within the watchdog timer monitoring time (tWD), the
CTW pin voltage falls below the Lo level (V_L) so the reset signal is output (RESET pin voltage changes from H
level to the L level).
The V_L value is about 0.24 V.
The watchdog timer monitoring time (t_WD) is expressed by the following equation.
t_WD [ms] » B x C_TW [mF]
B » 1600
(7) When the C_TP is recharged to raise the C_TP pin voltage above Vth, the reset clears, allowing the watchdog timer
to start running.
The watchdog timer monitoring reset time (t_WR) is expressed by the following equation.
t_WR [ms] » D x C_TP [mF]
B » 50
(8) When
signal
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pin
voltage
falls
so
that
the
reset
The V_SL value is about 2.75 V.
(9) When the OUT1 rises above V_SH, C_TP charging starts.
(10) When the C_TP pin voltage rises above Vth, the reset clears, causing the watchdog timer to start running.
(11) When the inhibit signal is input (Hi level), the watchdog timer operation is forcibly stopped.
In this case, only the watchdog timer stops and the OUT1 monitoring operations ((8) to (10)) are performed. If
the inhibit input does not clear, the watchdog timer does not operate.
(12) When the inhibit input clears (becomes Lo level), the watchdog timer begins to operate.
(13) When the REG1 output turns OFF and OUT1 falls below V_SL, the reset signal is output.
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