MB85RC64PNF-G Datasheet, PDF (14/20 Pages) Fujitsu Component Limited. – 64 K (8 K × 8) Bit I2C

MB85RC64
■ POWER ON SEQUENCE
tpd
VCC
2.7 V
VIH (Min)
tr
tpu
VCC
2.7 V
VIH (Min)
1.0 V
VIL (Max)
1.0 V
VIL (Max)
0V
0V
SDA, SCL
SDA, SCL >VCC × 0.8 ^*
* : SDA, SCL (Max) < VCC + 0.5 V
SDA, SCL : Don't care SDA, SCL >VCC × 0.8 ^* SDA, SCL
Parameter
SDA, SCL level hold time during power down
SDA, SCL level hold time during power up
Power supply rise time
Symbol
tpd
tpu
tr
Value
Unit
Min
Max
85
⎯
ns
85
⎯
ns
10
⎯
μs
■ NOTES ON USE
• Data written before performing IR reflow is not guaranteed.
• VDD pin is required to be rising from 0 V because turning the power on from an intermediate level may
cause malfunctions, when the power is turned on.
During the access period from the start condition to the stop condition, keep the level of WP, A0, A1, and
A2 pins to “H” or “L”.
14
DS05–13109–3E