MB15F07SL Datasheet, PDF (13/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

s PHASE COMPARATOR OUTPUT WAVEFORM
fr1/
fr2
fp1/
fp2
LD
tWU
tWL
(FC bit = High)
DO1/
DO2
(FC bit = Low)
DO1/
DO2
MB15F07SL
LD Output Logic Table
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Notes: • Phase error detection range = –2π to +2π
• Pulses on Do1/2 signals are output to prevent dead zone.
• LD output becomes low when phase error is tWU or more.
• LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
• tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when fosc = 12.8 MHz
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