MB15F07SL Datasheet, PDF (10/27 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer

MB15F07SL
Table 4. Binary 11-bit Programmable Counter Data Setting
Divide ratio
(N)
N11 N10 N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
00
0
00
0
11
4
0
0
0
00
0
00
1
00
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
2047
1
1
1
11
1
11
1
11
Note: Divide ratio less than 3 is prohibited.
Table 5. Binary 7-bit Swallow Counter Data Setting
Divide ratio
(N)
A7 A6 A5 A4 A3 A2 A1
0
0000000
1
0000001
⋅
⋅
⋅
⋅
⋅
⋅
⋅
⋅
127
1111111
Note: Divide ratio (A) range = 0 to 127
Table 6. Prescaler Data Setting
SW = “H”
Prescaler
divide ratio
PLL 1
PLL 2
64/65
64/65
SW = “L”
128/129
128/129
Table 7. Phase Comparator Phase Switching Data Setting
FC1, FC2 = “H” FC1, FC2 = “L”
Do1, Do2
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO Output
Frequency
VCO polarity
(1)
(2)
Note: • Z = High-impedance
• Depending upon the VCO and LPF polarity, FC bit should be set.
(1)
(2)
LPF Output Voltage
10