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MB15F03SL Datasheet, PDF (13/25 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer | |||
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s PHASE COMPARATOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DOIF/RF
Z
L
(FC bit = Low)
DOIF/RF
Z
MB15F03SL
LD Output Logic Table
IF-PLL section
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
Unlocking state
RF-PLL section
Locking state/Power saving state
Unlocking state
Locking state/Power saving state
Unlocking state
LD output
H
L
L
L
Notes: ⢠Phase error detection range = â2Ï to +2Ï
⢠Pulses on DoIF/RF signals are output to prevent dead zone.
⢠LD output becomes low when phase error is tWU or more.
⢠LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
⢠tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i. e. tWU > 156.3 ns when foscin = 12.8 MHz
tWU < 4/fosc: i. e. tWL < 312.5 ns when foscin = 12.8 MHz
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