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MB15F03SL Datasheet, PDF (10/25 Pages) Fujitsu Component Limited. – Dual Serial Input PLL Frequency Synthesizer | |||
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MB15F03SL
Table.4 Brinary 11-bit Programmable Counter Data Setting
Divide
ratio
(N)
NNNNNNNNNNN
11 10 9 8 7 6 5 4 3 2 1
3
4
â
2047
00000000011
00000000100
â
â
â
â
â
â
â
â
â
â
â
11111111111
Note: Divide ratio less than 3 is prohibited.
Table.5 Brinary 7-bit Swallow Counter Data Setting
Divide
ratio
(N)
AAAAAAA
7654321
0
0000000
1
0000001
â
â
â
â
â
â
â
â
127
1111111
Note: Divide ratio (A) range = 0 to 127
Table.6 Prescaler Data Setting
SW = âHâ
Prescaler
divide ratio
IF-PLL
RF-PLL
8/9
64/65
SW = âLâ
16/17
128/129
Table.7 Phase Comparator Phase Switching Data Setting
FCIF, RE = H
FCIF, RE = L
DoIF, RF
fr > fp
H
L
fr = fp
Z
Z
fr < fp
L
H
VCO Output
Frequency
VCO polarity
(1)
(2)
Note: Z = High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
(1)
(2)
LPF Output Voltage
Table.8 LD/fout Output Select Data Setting
LDS
LD/fout output signal
H
fout (frIF/RF, fpIF/RF) signals
L
LD signal
10
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