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MB40C328 Datasheet, PDF (12/16 Pages) Fujitsu Component Limited. – 8-bit 100 MSPS A/D Converter | |||
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MB40C328
s TIMING CHART 4
Two-phase CLK input mode (CLKA, CLKB)
⢠CLK = âLâ (DVSS) or âHâ (DVDD)
⢠CLKA = CLKB = 50 MHz (max)
⢠CKSEL = âLâ (AVSS)
⢠DSEL = âLâ (DVSS)
⢠RESET = âHâ (DVDD) or âLâ (DVSS)
⢠CE = âLâ (AVSS)
⢠OE = âLâ (DVSS)
VIHD
CLKA input
VILD
VIHD
CLKB input
VILD
DA0 to DA7
tWDâ
tWD+
N(Ach)
tWD+
tr
tf
DVDD â 0.5 V
0.5 V
1.5 V
tWDâ
tr
tf
DVDD â 0.5 V
0.5 V
1.5 V
N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch)
VINA input
tAD
tAD
VOHD
DA0 to DA7
VOLD
VOHD
DB0 to DB7
VOLD
Nâ6
Nâ4
Nâ5
VOHD
CLKOA
VOLD
VOHD
CLKOB
VOLD
Nâ3
tpdD(max)
tpdD(typ)
tpdD(min)
N
Nâ2
DVDDâ0.4 V
0.4 V
tpdD(max)
tpdD(typ)
tpdD(min)
N+1
Nâ1
tpdDO(max)
tpdDO(typ)
tpdDO(min)
DVDD â 0.4 V
0.4 V
DVDD â 0.4 V
0.4 V
tpdDO(max.)
tpdDO(typ)
tpdDO(min.)
DVDD â 0.4 V
0.4 V
⢠VINA input â Sampling (A ch) at CLKA falling
Sampling (B ch) at CLKB falling
⢠DA0 to DA7 â Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising
⢠DB0 to DB7 â Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising
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