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MB40C328 Datasheet, PDF (10/16 Pages) Fujitsu Component Limited. – 8-bit 100 MSPS A/D Converter | |||
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MB40C328
s TIMING CHART 2
CLK input-demultiplex output (in-phase) mode
⢠CLK = 100 MHz (max)
⢠CLKA = CLKB = âLâ (DVSS)
⢠CKSEL = âHâ (AVDD)
⢠DSEL = âLâ (DVSS)
⢠CE = âLâ (AVSS)
⢠OE = âLâ (DVSS)
VIHD
CLK input
VILD
tr
tf
T
tWS+ tWSâ
DVDD â 0.5 V
0.5 V
1.5 V
Nâ1 Nâ2 Nâ1 N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10
VINA input
tAD
Nâ9 Nâ9
VOHD or N â 10 or N â 8
DA0 to DA7
VOLD
Nâ7
or N â 8
N â 10 N â 10 N â 8 N â 8
VOHD or N â 11 or N â 9or N â 9 or N â 7
DB0 to DB7
VOLD
Nâ5
or N â 6
Nâ6
or N â 7
VOHD
CLKOA
VOLD
Nâ3
or N â 4
Nâ4
or N â 5
tpdM1(max)
tpdM1(typ)
tpdM1(min)
N+1
Nâ1
or N â 2
DVDD â 0.4 V
0.4V
tpdM1(max)
tpdM1(typ)
tpdM1(min)
N
Nâ2
DVDD â 0.4 V
or N â 3 0.4V
tpdM1O(max)
tpdM1O(typ)
tpdM1O(min)
N+3
N+2
DVDD â 0.4 V
0.4 V
VOHD
CLKOB
VOLD
VIHD
RESET input
VILD
th tS th tS
1.5 V
ALL âLâ fix
⢠VINA input â Sampling at CLK rising
⢠DA0 to DA7 â Output (after 5 CLK + tpdM1 from Sampling) at CLK rising
⢠DB0 to DB7 â Output (after 6 CLK + tpdM1 from Sampling) at CLK rising
10
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