MB40C328 Datasheet, PDF (11/16 Pages) Fujitsu Component Limited. – 8-bit 100 MSPS A/D Converter

MB40C328
s TIMING CHART 3
CLK input-demultiplex output (two-phase) mode
• CLK = 100 MHz (max)
• CLKA = CLKB = “L” (DVSS)
• CKSEL = “L” (AVSS)
• DSEL = “H” (DVDD)
• CE = “L” (AVSS)
• OE = “L” (DVSS)
VIHD
CLK input
VILD
tr
tf
T
DVDD − 0.5 V
0.5 V
tWS⁺ tWS^−
1.5 V
N−3 N−2 N−1 N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10
VINA input
tAD
tpdM2(max)
tpdM2(typ)
N−9 N−9
VOHD ^{or N − 10 or N − 8}
DA0 to DA7
VOLD
N−7
or N − 8
N−5
or N − 6
tpdM2(min)
N−3
N−1
or N − 4
or N − 2
tpdM2(max)
N+1
DVDD − 0.4 V
0.4 V
N+3
N − 10 N − 8 N − 8
VOHD ^{or N − 9 or N − 9 or N − 7}
DB0 to DB7
VOLD
N−6
or N − 7
N−4
or N − 5
tpdM2(typ)
tpdM2(min)
N−2
or N − 3
N
DVDD−0.4 V
0.4 V
tpdM2O(max)
N+2
tpdM2O(typ)
VOHD
CLKOA
VOLD
tpdM2O(min)
DVDD − 0.4 V
0.4 V
tpdM2O(max)
tpdM2O(typ)
VOHD
CLKOB
VOLD
tpdM2O(min)
DVDD − 0.4 V
0.4 V
VIHD
RESET input
VILD
th tS th tS
1.5 V
• VINA input — Sampling at CLK rising
• DA0 to DA7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
• DB0 to DB7 — Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
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