UMFT230XA-02 Datasheet, PDF (7/21 Pages) Future Technology Devices International Ltd. – UMFT230XA USB to Basic UART Development Module

UMFT230XA Datasheet
Version 1.4
D oc ument Reference N o.: FT _000519 C learance N o.: FT DI# 2 6 9
4.3 CBUS Signal Options
The following options can be configured on the CBUS I/O pins. These options are all configured in the
internal MTP ROM using the utility software FT_PROG, which can be downloaded from the
www.ftdichip.com. The default configuration is described in DS_UMFT231XA.
CBUS Signal
Option
Tristate
TXDEN
DRIVE_1
DRIVE_0
PWREN#
TXLED#
RXLED#
TX&RXLED#
SLEEP#
C LK24MHz
C LK12MHz
C LK6MHz
GPIO
BC D_C harger
BC D_C harger#
BitBang_WR#
BitBang_RD#
VBUS Sense
Time Stamp
Keep_Awake#
Available On
CBUS Pin
Description
C BUS0-C BUS3 IO Pad is tristated
C BUS0-C BUS3 Enable transmit data for RS485
C BUS0-C BUS3 Output a constant 1
C BUS0-C BUS3 Output a constant 0
C BUS0-C BUS3
Output is low after the device has been configured by USB, then high during
USB suspend mode. This output can be used to control power to exte rnal logic
P-C hannel logic level MOSFET switch.
NOTE: This function is driven by an open-drain to ground with no internal
pull-up; this is specially designed to aid battery charging applications.
UMFT230XA connects an on-board 47K pull-up to each CBUS and DBUS pin.
C BUS0-C BUS3
Transmit data LED drive – open drain pulses low when transmitting data via
USB.
C BUS0-C BUS3 Receive data LED drive – open drain pulses low when receiving data via USB.
C BUS0-C BUS3
LED drive – open drain pulses low when transmitting or receiving data via
USB.
C BUS0-C BUS3
Goes low during USB suspend mode. Typically used to power down an
external logic to RS232 level converter IC in USB to RS232 converter designs.
C ancel SLEEP# option for when connected to a dedicated charger port, this
can be selected when configuring the MTP ROM. When this option is enabled
SLEEP# is driven high when FT230X is connected to a Dedicated Charger Port.
C BUS0-C BUS3 24 MHz C lock output.**
C BUS0-C BUS3 12 MHz C lock output.**
C BUS0-C BUS3 6 MHz C lock output.**
C BUS0-C BUS3
C BUS bit bang mode option. Allows up to 4 of the C BUS pins to be used as
general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and
C BUS3 in the internal MTP ROM. A separate application note, AN232R-01,
available from FTDI website (www.ftdichip.com) describes in more detail how
to use C BUS bit bang mode.
C BUS0-C BUS3
Battery C harge Detect indicates when the device is connected to a dedicated
battery charger host. Active high output. NOTE: Requires a 10K pull-down to
remove power up toggling.
C BUS0-C BUS3
Active low BCD Charger, driven by an open drain to ground with no internal
pull-up (4.7K on board pull-up present).
C BUS0-C BUS3 Synchronous and asynchronous bit bang mode WR# strobe output.
C BUS0-C BUS3 Synchronous and asynchronous bit bang mode RD# strobe output.
C BUS0-C BUS3 Input to detect when VBUS is present.
C BUS0-C BUS3 Toggle signal which changes state each time a USB SOF is received
C BUS0-C BUS3 Active Low input, prevents the chip from going into suspend.
Table 4.2 – CBUS Signal Options
**When in USB suspend mode the outputs clocks are also suspended .
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