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MC9S08DZ60MLC Datasheet, PDF (99/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features | |||
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6.5.3.3 Port C Pull Enable Register (PTCPE)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTCPE7
0
6
PTCPE6
5
PTCPE5
4
PTCPE4
3
PTCPE3
2
PTCPE2
1
PTCPE1
0
0
0
0
0
0
Figure 6-21. Internal Pull Enable for Port C Register (PTCPE)
Table 6-19. PTCPE Register Field Descriptions
0
PTCPE0
0
Field
Description
7:0
PTCPE[7:0]
Internal Pull Enable for Port C Bits â Each of these control bits determines if the internal pull-up device is
enabled for the associated PTC pin. For port C pins that are conï¬gured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port C bit n.
1 Internal pull-up device enabled for port C bit n.
NOTE
Pull-down devices only apply when using pin interrupt functions, when
corresponding edge select and pin select functions are conï¬gured.
6.5.3.4 Port C Slew Rate Enable Register (PTCSE)
R
W
Reset:
7
PTCSE7
0
6
PTCSE6
5
PTCSE5
4
PTCSE4
3
PTCSE3
2
PTCSE2
1
PTCSE1
0
0
0
0
0
0
Figure 6-22. Slew Rate Enable for Port C Register (PTCSE)
Table 6-20. PTCSE Register Field Descriptions
0
PTCSE0
0
Field
Description
7:0
PTCSE[7:0]
Output Slew Rate Enable for Port C Bits â Each of these control bits determines if the output slew rate control
is enabled for the associated PTC pin. For port C pins that are conï¬gured as inputs, these bits have no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
Note: Slew rate reset default values may differ between engineering samples and ï¬nal production parts. Always initialize slew
rate control to the desired value to ensure correct operation.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
99
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