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MC9S08DZ60MLC Datasheet, PDF (233/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
TXE2
TXE1
TXE0
W
Reset:
0
0
0
0
0
1
1
1
= Unimplemented
Figure 12-10. MSCAN Transmitter Flag Register (CANTFLG)
NOTE
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Read: Anytime
Write: Anytime for TXEx ï¬ags when not in initialization mode; write of 1 clears ï¬ag, write of 0 is ignored
Table 12-11. CANTFLG Register Field Descriptions
Field
2:0
TXE[2:0]
Description
Transmitter Buffer Empty â This ï¬ag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the ï¬ag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the ï¬ag after the message is sent successfully. The ï¬ag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 12.3.8, âMSCAN Transmitter Message Abort Request Register (CANTARQ)â). If not masked, a transmit
interrupt is pending while this ï¬ag is set.
Clearing a TXEx ï¬ag also clears the corresponding ABTAKx (see Section 12.3.9, âMSCAN Transmitter Message
Abort Acknowledge Register (CANTAAK)â). When a TXEx ï¬ag is set, the corresponding ABTRQx bit is cleared
(see Section 12.3.8, âMSCAN Transmitter Message Abort Request Register (CANTARQ)â).
When listen-mode is active (see Section 12.3.2, âMSCAN Control Register 1 (CANCTL1)â) the TXEx ï¬ags cannot
be cleared and no transmission is started.
Read and write accesses to the transmit buffer are blocked, if the corresponding TXEx bit is cleared (TXEx = 0)
and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
12.3.7 MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt ï¬ags.
R
W
Reset:
7
6
5
4
3
2
1
0
0
0
0
0
TXEIE2
TXEIE1
0
0
0
0
0
0
0
= Unimplemented
Figure 12-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
0
TXEIE0
0
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
233
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