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MC9S08DZ60MLC Datasheet, PDF (237/416 Pages) Freescale Semiconductor, Inc – MC9S08DZ60 Series Features | |||
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Chapter 12 Freescaleâs Controller Area Network (S08MSCANV1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1), except bits IDHITx, which are
read-only
Table 12-16. CANIDAC Register Field Descriptions
Field
Description
5:4
IDAM[1:0]
2:0
IDHIT[2:0]
Identiï¬er Acceptance Mode â The CPU sets these ï¬ags to deï¬ne the identiï¬er acceptance ï¬lter organization
(see Section 12.5.3, âIdentiï¬er Acceptance Filterâ). Table 12-17 summarizes the different settings. In ï¬lter closed
mode, no message is accepted such that the foreground buffer is never reloaded.
Identiï¬er Acceptance Hit Indicator â The MSCAN sets these ï¬ags to indicate an identiï¬er acceptance hit (see
Section 12.5.3, âIdentiï¬er Acceptance Filterâ). Table 12-18 summarizes the different settings.
IDAM1
0
0
1
1
Table 12-17. Identiï¬er Acceptance Mode Settings
IDAM0
0
1
0
1
Identiï¬er Acceptance Mode
Two 32-bit acceptance ï¬lters
Four 16-bit acceptance ï¬lters
Eight 8-bit acceptance ï¬lters
Filter closed
Table 12-18. Identiï¬er Acceptance Hit Indication
IDHIT2
IDHIT1
IDHIT0
Identiï¬er Acceptance Hit
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Filter 0 hit
Filter 1 hit
Filter 2 hit
Filter 3 hit
Filter 4 hit
Filter 5 hit
Filter 6 hit
Filter 7 hit
The IDHITx indicators are always related to the message in the foreground buffer (RxFG). When a
message gets shifted into the foreground buffer of the receiver FIFO the indicators are updated as well.
12.3.12 MSCAN Miscellaneous Register (CANMISC)
This register provides additional features.
MC9S08DZ60 Series Data Sheet, Rev. 4
Freescale Semiconductor
237
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