MC56F8335 Datasheet, PDF (99/160 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controller

Operating Modes
6.3 Operating Modes
Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the
various chip operating modes and take appropriate action. These are:
• Reset Mode, which has two submodes:
— POR and RESET operation
The 56800E core and all peripherals are reset. This occurs when the internal POR is asserted or the
RESET pin is asserted.
— COP reset and software reset operation
The 56800E core and all peripherals are reset. The MA bit within the OMR is not changed. This allows
the software to determine the boot mode (internal or external boot) to be used on the next reset.
• Run Mode
This is the primary mode of operation for this device. In this mode, the 56800E controls chip operation.
• Debug Mode
The 56800E is controlled via JTAG/EOnCE when in debug mode. All peripherals, except the COP and
PWMs, continue to run. COP is disabled and PWM outputs are optionally switched off to disable any motor
from being driven; see the PWM chapter in the 56F8300 Peripheral User Manual for details.
• Wait Mode
In Wait mode, the core clock and memory clocks are disabled. Optionally, the COP can be stopped.
Similarly, it is an option to switch off PWM outputs to disable any motor from being driven. All other
peripherals continue to run.
• Stop Mode
When in Stop mode, the 56800E core, memory and most peripheral clocks are shut down. Optionally, the
COP and CAN can be stopped. For lowest power consumption in Stop mode, the PLL can be shut down.
This must be done explicitly before entering Stop mode, since there is no automatic mechanism for this. The
CAN (along with any non-gated interrupt) is capable of waking the chip up from Stop mode, but is not fully
functional in Stop mode.
6.4 Operating Mode Register
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
NL
CM XP SD
R
SA EX
0
MB MA
Type
R/W
R/W R/W R/W R/W R/W R/W
R/W R/W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
Figure 6-1 OMR
The reset state for MB and MA will depend on the Flash secured state. See Part 4.2 and Part 7 for detailed
information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For
additional information on the EX bit, see Part 4.4. For all other bits, see the DSP56F800E Reference
Manual.
Note: The OMR is not a Memory Map register; it is directly accessible in code through the acronym OMR.
56F8335 Technical Data, Rev. 1
Freescale Semiconductor
99
Preliminary