MC56F8335 Datasheet, PDF (92/160 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controller

5.6.14 Fast Interrupt 0 Vector Address High Register (FIVAH0)
Base + $D
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
Write
0
0
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 0
VECTOR ADDRESS HIGH
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-16 Fast Interrupt 0 Vector Address High Register (FIVAH0)
5.6.14.1 Reserved—Bits 15–5
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.14.2 Fast Interrupt 0 Vector Address High (FIVAH0)—Bits 4–0
The upper five bits of the vector address used for Fast Interrupt 0. This register is combined with FIVAL0
to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register.
5.6.15 Fast Interrupt 1 Match Register (FIM1)
Base + $E
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
Write
0
0
0
0
0
0
0
0
0
FAST INTERRUPT 1
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-17 Fast Interrupt 1 Match Register (FIM1)
5.6.15.1 Reserved—Bits 15–7
This bit field is reserved or not implemented. It is read as 0, but cannot be modified by writing.
5.6.15.2 Fast Interrupt 1 Vector Number (FAST INTERRUPT 1)—Bits 6–0
This value determines which IRQ will be a Fast Interrupt 1. Fast interrupts vector directly to a service
routine based on values in the Fast Interrupt Vector Address registers without having to go to a jump table
first; see Part 5.3.3. IRQs used as fast interrupts must be set to priority level 2. Unexpected results will
occur if a fast interrupt vector is set to any other priority. Fast interrupts automatically become the
highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared
as fast interrupt. Fast Interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each
IRQ, refer to Table 4-5.
56F8335 Technical Data, Rev. 1
92
Freescale Semiconductor
Preliminary