MCIMX31 Datasheet, PDF (97/170 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors

Electrical Characteristics
Table 35. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
SD13 Data setup time
tDS
SD14 Data hold time
tDH
1 _{SD11 and SD12 are determined by SDRAM controller register settings.}
2.0
–
ns
1.3
–
ns
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
SDCLK
SDCLK
CS
SD1
SD2
SD3
RAS
CAS
SD11
WE
ADDR
SD7
SD6
BA
DQ
DQM
SD10
SD10
ROW/BA
Figure 38. SDRAM Refresh Timing Diagram
Table 36. SDRAM Refresh Timing Parameters
ID
Parameter
SD1 SDRAM clock high-level width
SD2 SDRAM clock low-level width
Symbol
Min
tCH
3.4
tCL
3.4
Freescale Semiconductor
i.MX31/i.MX31L Advance Information, Rev. 1.4
Preliminary
Max
Unit
4.1
ns
4.1
ns
97