MCIMX31 Datasheet, PDF (111/170 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processors

Electrical Characteristics
4.3.15.3 Interface to Sharp HR-TFT Panels
Figure 52 depicts the Sharp HR-TFT panel interface timing, and Table 50 lists the timing parameters. The
CLS_RISE_DELAY, CLS_FALL_DELAY, PS_FALL_DELAY, PS_RISE_DELAY,
REV_TOGGLE_DELAY parameters are defined in the SDC_SHARP_CONF_1 and
SDC_SHARP_CONF_2 registers. For other Sharp interface timing characteristics, refer to
Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical Characteristics” on page 108.
The timing images correspond to straight polarity of the Sharp signals.
Horizontal timing
DISPB_D3_CLK
DISPB_D3_DATA
D1 D2
D320
DISPB_D3_SPL
DISPB_D3_HSYNC
DISPB_D3_CLS
DISPB_D3_PS
IP21
1 DISPB_D3_CLK period
IP22
IP23
IP24
DISPB_D3_REV
IP25
IP26
Example is drawn with FW+1=320 pixel/line, FH+1=240 lines.
SPL pulse width is fixed and aligned to the first data of the line.
REV toggles every HSYNC period.
Figure 52. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level
Table 50. Sharp Synchronous Display Interface Timing Parameters—Pixel Level
ID
IP21
IP22
IP23
IP24
Parameter
SPL rise time
CLS rise time
CLS fall time
CLS rise and PS fall time
Symbol
Tsplr
Tclsr
Tclsf
Tpsf
Value
(BGXP - 1) * Tdpcp
CLS_RISE_DELAY * Tdpcp
CLS_FALL_DELAY * Tdpcp
PS_FALL_DELAY * Tdpcp
Units
ns
ns
ns
ns
i.MX31/i.MX31L Advance Information, Rev. 1.4
Freescale Semiconductor
111
Preliminary