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| MC9S12DT128 Datasheet, PDF (89/142 Pages) Freescale Semiconductor, Inc – Device User Guide | |||
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Device User Guide â 9S12DT128DGV2/D V02.15
Section 21 Port Integration Module (PIM) Block Description
Consult the PIM_9DTB128 Block User Guide for information about the Port Integration Module.
Section 22 Voltage Regulator (VREG) Block Description
Consult the VREG Block User Guide for information about the dual output linear voltage regulator.
Section 23 Printed Circuit Board Layout Proposal
Table 23-1 Suggested External Component Values
Component
C1
C2
C3
C4
C5
C6
C7
C8
C9 / CS
C10 / CP
C11 / CDC
R1 / R
R2 / RB
R3 / RS
Q1
Purpose
VDD1 ï¬lter cap
VDD2 ï¬lter cap
VDDA ï¬lter cap
VDDR ï¬lter cap
VDDPLL ï¬lter cap
VDDX ï¬lter cap
OSC load cap
OSC load cap
PLL loop ï¬lter cap
PLL loop ï¬lter cap
DC cutoff cap
PLL loop ï¬lter res
Quartz
Type
ceramic X7R
ceramic X7R
ceramic X7R
X7R/tantalum
ceramic X7R
X7R/tantalum
Value
100 ⦠220nF
100 ⦠220nF
100nF
>= 100nF
100nF
>= 100nF
See PLL speciï¬cation chapter
Colpitts mode only, if recommended by
quartz manufacturer
See PLL Speciï¬cation chapter
Pierce mode only
The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the
MCU itself. The following rules must be observed:
⢠Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the
corresponding pins (C1 â C6).
⢠Central point of the ground star should be the VSSR pin.
Freescale Semiconductor
89
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