DSP56L307 Datasheet, PDF (89/104 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

page 132,55,0,0,0
opt mex
ioequ ident 1,0
;------------------------------------------------------------------------
;
;
EQUATES for I/O Port Programming
;
;------------------------------------------------------------------------
;
Register Addresses
M_HDR EQU $FFFFC9
M_HDDR EQU $FFFFC8
M_PCRC EQU $FFFFBF
M_PRRC EQU $FFFFBE
M_PDRC EQU $FFFFBD
M_PCRD EQU $FFFFAF
M_PRRD EQU $FFFFAE
M_PDRD EQU $FFFFAD
M_PCRE EQU $FFFF9F
M_PRRE EQU $FFFF9E
M_PDRE EQU $FFFF9D
M_OGDB EQU $FFFFFC
; Host port GPIO data Register
; Host port GPIO direction Register
; Port C Control Register
; Port C Direction Register
; Port C GPIO Data Register
; Port D Control register
; Port D Direction Data Register
; Port D GPIO Data Register
; Port E Control register
; Port E Direction Register
; Port E Data Register
; OnCE GDB Register
;------------------------------------------------------------------------
;
;
EQUATES for Host Interface
;
;------------------------------------------------------------------------
;
Register Addresses
M_HCR EQU $FFFFC2
M_HSR EQU $FFFFC3
M_HPCR EQU $FFFFC4
M_HBAR EQU $FFFFC5
M_HRX EQU $FFFFC6
M_HTX EQU $FFFFC7
; Host Control Register
; Host Status Register
; Host Polarity Control Register
; Host Base Address Register
; Host Receive Register
; Host Transmit Register
;
HCR bits definition
M_HRIE EQU $0
M_HTIE EQU $1
M_HCIE EQU $2
M_HF2 EQU $3
M_HF3 EQU $4
; Host Receive interrupts Enable
; Host Transmit Interrupt Enable
; Host Command Interrupt Enable
; Host Flag 2
; Host Flag 3
;
HSR bits definition
M_HRDF EQU $0
M_HTDE EQU $1
M_HCP EQU $2
M_HF0 EQU $3
M_HF1 EQU $4
; Host Receive Data Full
; Host Receive Data Empty
; Host Command Pending
; Host Flag 0
; Host Flag 1
;
HPCR bits definition
M_HGEN EQU $0
M_HA8EN EQU $1
M_HA9EN EQU $2
M_HCSEN EQU $3
; Host Port GPIO Enable
; Host Address 8 Enable
; Host Address 9 Enable
; Host Chip Select Enable
DSP56L307 Technical Data, Rev. 6
Freescale Semiconductor
A-5