DSP56L307 Datasheet, PDF (33/104 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

AC Electrical Characteristics
Table 2-8. 100 MHz SRAM Timing (Continued)
100 MHz
No.
Characteristics
Symbol
Expression¹
Unit
Min Max
Notes: 1. WS = number of BCR-specified wait states. The value is the minimum for a given category. (for example, for a category of [2 ≤
WS ≤7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise.
2. Timings 100 and 107 are guaranteed by design, not tested.
3. All timings for 160 MHz are measured from 0.5 × V_CCH to 0.5 × V_CCH.
4. For TA deassertion: timing 118 is relative to the deassertion edge of RD or WR if TA is active.
5. The WS number applies to the access in which the deassertion of WR occurs and assumes the next access uses a minimal
number of wait states.
Table 2-9. 160 MHz SRAM Timing
No.
Characteristics
100 Address valid and AA assertion pulse width²
101 Address and AA valid to WR assertion
102 WR assertion pulse width
103 WR deassertion to address not valid
104 Address and AA valid to input data valid
105 RD assertion to input data valid
106 RD deassertion to data not valid (data hold time)
107 Address valid to WR deassertion²
108 Data valid to WR deassertion (data set-up time)
109 Data hold time from WR deassertion
110 WR assertion to data active
111 WR deassertion to data high impedance
Symbol
Expression¹
160 MHz
Unit
Min Max
t_RC, t_WC
(WS + 2) × T_C −4.0
21.0
—
ns
[2 ≤WS ≤7]
(WS + 3) × T_C −4.0 64.7
—
ns
[WS ≥ 8]
t_AS
0.75 × T_C −3.0
1.7
—
ns
[2 ≤WS ≤3]
1.25 × T_C −3.0
[WS ≥ 4]
4.8
—
ns
t_WP
WS × T_C −4.0
8.5
—
ns
[2 ≤WS ≤3]
(WS −0.5) × T_C −4.0 17.8
—
ns
[WS ≥ 4]
t_WR
1.25 × T_C −4.0
3.8
—
ns
[2 ≤WS ≤7]
2.25 × T_C −4.0
[WS ≥ 8]
10.0
—
ns
t_AA, t_AC (WS + 0.75) × T_C −6.5 —
[WS ≥ 2]
10.7 ns
t_OE
(WS + 0.25) × T_C −6.5 —
[WS ≥ 2]
7.6
ns
t_OHZ
0.0
—
ns
t_AW
(WS + 0.75) × T_C −4.0 13.2
—
ns
[WS ≥ 2]
t_DS (t_DW) (WS −0.25) × T_C −5.4 5.5
[WS ≥ 2]
—
ns
t_DH
1.25 × T_C −4.0
3.8
—
ns
[2 ≤WS ≤7]
2.25 × T_C −4.0
[WS ≥ 8]
10.1
—
ns
—
0.25 × T_C −4.0
–2.4
—
ns
[2 ≤WS ≤3]
-0.25 × T_C −4.0
[WS ≥ 4]
–5.6
—
ns
—
1.25 × T_C
—
7.8
ns
[2 ≤WS ≤7]
2.25 × T_C
[WS ≥ 8]
—
14.0
Freescale Semiconductor
DSP56L307 Technical Data, Rev. 6
2-13