DSP56L307 Datasheet, PDF (59/104 Pages) Motorola, Inc – 24-Bit Digital Signal Processor

ESSI0/ESSI1 Timing
Table 2-19. ESSI Timings at 100 MHz (Continued)
No.
Characteristics^{1, 2, 3}
Symbol
Expression
Min
Max
Condi-
tion⁴
Unit
451 TXC rising edge to FST out (wl) low
—
—
— 31.0
x ck
ns
— 17.0
i ck
452 TXC rising edge to data out enable from high impedance
—
—
— 31.0
x ck
ns
— 17.0
i ck
453 TXC rising edge to transmitter 0 drive enable assertion
—
—
— 34.0
x ck
ns
— 20.0
i ck
454 TXC rising edge to data out valid
455 TXC rising edge to data out high impedance⁷
456 TXC rising edge to transmitter 0 drive enable deassertion⁷
457 FST input (bl, wr) set-up time before TXC falling edge⁶
—
35 + 0.5 × T_C
— 40.0
x ck
ns
— 21.0
i ck
—
—
— 31.0
x ck
ns
— 16.0
i ck
—
—
— 34.0
x ck
ns
— 20.0
i ck
—
—
2.0 —
x ck
ns
21.0 —
i ck
458 FST input (wl) to data out enable from high impedance
—
—
— 27.0
—
ns
459 FST input (wl) to transmitter 0 drive enable assertion
—
—
— 31.0
—
ns
460 FST input (wl) set-up time before TXC falling edge
—
—
2.0 —
x ck
ns
21.0 —
i ck
461 FST input hold time after TXC falling edge
—
—
4.0 —
x ck
ns
0.0 —
i ck
462 Flag output valid after TXC rising edge
—
—
— 32.0
x ck
ns
— 18.0
i ck
Notes: 1. V_CCQL = 2.5 V ± 0.25 V; T_J = −40°C to +100 °C, C_L = 50 pF
2. i ck = Internal Clock
x ck = External Clock
i ck a = Internal Clock, Asynchronous Mode
(Asynchronous implies that TXC and RXC are two different clocks)
i ck s = Internal Clock, Synchronous Mode
(Synchronous implies that TXC and RXC are the same clock)
3. bl = bit length
wl = word length
wr = word length relative
4. TXC (SCK Pin) = Transmit Clock
RXC (SC0 or SCK Pin) = Receive Clock
FST (SC2 Pin) = Transmit Frame Sync
FSR (SC1 or SC2 Pin) Receive Frame Sync
5. For the internal clock, the external clock cycle is defined by Icyc and the ESSI control register.
6. The word-relative frame sync signal waveform relative to the clock operates the same way as the bit-length frame sync signal
waveform, but it spreads from one serial clock before first bit clock (same as Bit Length Frame Sync signal), until the one
before last bit clock of the first word in frame.
7. Periodically sampled and not 100 per cent tested
Freescale Semiconductor
DSP56L307 Technical Data, Rev. 6
2-39