MC9S08SH8CTJ Datasheet, PDF (86/341 Pages) Freescale Semiconductor, Inc – MC9S08SH8 Datasheet

Chapter 6 Parallel Input/Output Control
6.6.1.4 Port A Slew Rate Enable Register (PTASE)
7
R
0
W
Reset:
0
6
5
4
3
2
1
0
R
PTASE4
PTASE3
PTASE2
PTASE1
0
0
0
0
0
0
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-5. PTASE Register Field Descriptions
0
PTASE0
0
Field
Description
5
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Reserved
4:0
PTASE[4:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
6.6.1.5 Port A Drive Strength Selection Register (PTADS)
7
6
5
4
3
2
1
0
R
0
0
R
PTADS4
PTADS3
PTADS2
PTADS1
PTADS0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-7. Drive Strength Selection for Port A Register (PTADS)
Table 6-6. PTADS Register Field Descriptions
Field
Description
5
Reserved Bits — These bits are unused on this MCU, writes have no affect and could read as 1s or 0s.
Reserved
4:0
PTADS[4:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
MC9S08SH8 MCU Series Data Sheet, Rev. 3
82
Freescale Semiconductor