MC9S08SH8CTJ Datasheet, PDF (313/341 Pages) Freescale Semiconductor, Inc – MC9S08SH8 Datasheet

Appendix A Electrical Characteristics
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-13. Control Timing
Nu
m
C
Rating
Symbol
Min
Typ¹
Max Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2 D Internal low power oscillator period
t_LPO
800
1500 μs
3 D _{External reset pulse width}²
t_extrst
100
—
ns
4 D _{Reset low drive}³
t_rstdrv
66 x t_cyc
—
ns
Pin interrupt pulse width
8 D Asynchronous path²
Synchronous path⁵
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁴
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
9
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)⁶
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_ILIH, t_IHIL
100
—
1.5 x t_cyc
t_Rise, t_Fall
—
40
—
75
t_Rise, t_Fall
—
11
—
35
—
ns
—
ns
—
—
ns
—
1 _{Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of tcyc. After POR reset the bus clock}
frequency changes to the untrimmed DCO frequency (f_reset = (f_{dco_ut})/4) because TRIM is reset to 0x80 and FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
4 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
RESET PIN
t_extrst
Figure A-10. Reset Timing
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
309