MC9S08SH8CTJ Datasheet, PDF (307/341 Pages) Freescale Semiconductor, Inc – MC9S08SH8 Datasheet

Appendix A Electrical Characteristics
A.9 Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specification (Temperature Range = –40 to 125°C Ambient)
Nu
m
C
Rating
Symbol
Min
Typical
Max
Unit
Internal reference frequency - factory trimmed
1 P _{at VDD = 5 V and temperature = 25°C}
2 P _{Internal reference frequency - untrimmed}¹
3 P Internal reference frequency - user trimmed
4 D Internal reference startup time
5
—
DCO output frequency range - untrimmed¹
value provided for reference: f_{dco_ut} = 1024 × f_{int_ut}
6 D DCO output frequency range - trimmed
7
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
8
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
9
D
Total deviation from actual trimmed DCO output
frequency over voltage and temperature
10
D
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0°C to 70 °C
f_{int_ft}
f_{int_ut}
f_{int_t}
t_irefst
f_{dco_ut}
f_{dco_t}
Δf_{dco_res_t}
Δf_{dco_res_t}
Δf_{dco_t}
Δf_{dco_t}
—
25
31.25
—
25.6
32
—
—
—
—
31.25
36
—
55
36.86
—
± 0.1
± 0.2
+ 0.5
– 1.0
± 0.5
—
41.66
39.0625
100
42.66
40
± 0.2
± 0.4
±2
±1
kHz
kHz
kHz
μs
MHz
MHz
%f_dco
%f_dco
%f_dco
%f_dco
11 D _{FLL acquisition time} ²
t_acquire
1
ms
12 D _{DCO output clock long term jitter (over 2mS interval)} ³
C_Jitter
—
0.02
0.2
%f_dco
1 _{TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).}
2 _{This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing}
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
3 _{Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.}
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via V_DD and V_SS and variation in crystal oscillator frequency increase the C_Jitter percentage for a
given interval.
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Freescale Semiconductor
303