MC68332ACEH25 Datasheet, PDF (85/88 Pages) Freescale Semiconductor, Inc – Technical Summary 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
RASP — RAM Array Space Field
0 = TPURAM array is placed in unrestricted space
1 = TPURAM array is placed in supervisor space
TRAMTST — TPURAM Test Register
TRAMTST is used for factory testing of the TPURAM module.
$YFFB02
TRAMBAR — TPURAM Base Address and Status Register
15
ADDR
23
RESET:
0
14
ADDR
22
0
13
ADDR
21
0
12
ADDR
20
0
11
ADDR
19
0
10
ADDR
18
0
9
ADDR
17
0
8
ADDR
16
0
7
ADDR
15
0
6
ADDR
14
0
5
ADDR
13
0
4
ADDR
12
0
3
ADDR
11
0
$YFFB04
2
1
NOT USED
0
RAMDS
0
0
0
ADDR[23:11] — RAM Array Base Address
These bits specify address lines ADDR[23:11] of the base address of the RAM array when enabled.
RAMDS — RAM Array Disable
0 = RAM array is enabled
1 = RAM array is disabled
The RAM array is disabled by internal logic after a master reset. Writing a valid base address to the
RAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the RAM array.
7.4 TPURAM Operation
There are six TPURAM operating modes, as follows:
1. The TPURAM module is in normal mode when powered by V_DD. The array can be accessed
by byte, word, or long word. A byte or aligned word (high-order byte is at an even address) ac-
cess only takes one bus cycle or two system clocks. A long word or misaligned word access
requires two bus cycles.
2. Standby mode is intended to preserve TPURAM contents when V_DD is removed. TPURAM
contents are maintained by V_STBY. Circuitry within the TPURAM module switches to the higher
of V_DD or V_STBY with no loss of data. When TPURAM is powered by V_STBY, access to the array
is not guaranteed.
3. Reset mode allows the CPU to complete the current bus cycle before resetting. When a syn-
chronous reset occurs while a byte or word TPURAM access is in progress, the access will be
completed. If reset occurs during the first word access of a long-word operation, only the first
word access will be completed. If reset occurs during the second word access of a long word
operation, the entire access will be completed. Data being read from or written to the RAM may
be corrupted by asynchronous reset.
4. Test mode functions in conjunction with the SIM test functions. Test mode is used during factory
test of the MCU.
5. Writing the STOP bit of TRAMMCR causes the TPURAM module to enter stop mode. The
TPURAM array is disabled (which allows external logic to decode TPURAM addresses, if nec-
essary), but all data is retained. If V_DD falls below V_STBY during stop mode, internal circuitry
switches to V_STBY, as in standby mode. Stop mode is exited by clearing the STOP bit.
6. The TPURAM array may be used to emulate the microcode ROM in the TPU module. This pro-
vides a means of developing custom TPU code. The TPU selects TPU emulation mode. While
in TPU emulation mode, the access timing of the TPURAM module matches the timing of the
TPU microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are in-
hibited and the control registers have no effect, allowing external RAM to emulate the TPURAM
at the same addresses.
MC68332
MC68332TS/D
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