MC68332ACEH25 Datasheet, PDF (47/88 Pages) Freescale Semiconductor, Inc – Technical Summary 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
4.6 Instruction Set Summary
Instruction
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR1¹
ASL
ASR
Bcc
BCHG
BCLR
BGND
BKPT
BRA
BSET
BSR
BTST
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
Table 20 Instruction Set Summary
Syntax
Dn, Dn
− (An), − (An)
Dn, <ea>
<ea>, Dn
<ea>, An
#<data>, <ea>
# <data>, <ea>
Dn, Dn
− (An), − (An)
<ea>, Dn
Dn, <ea>
# <data>, <ea>
# <data>, CCR
# <data>, SR
Dn, Dn
# <data>, Dn
Í
Dn, Dn
# <data>, Dn
Í
Operand Size
8
8
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
Operation
Source₁₀ + Destination₁₀ + X ⇒ Destination
Source + Destination ⇒ Destination
Source + Destination ⇒ Destination
Immediate data + Destination ⇒ Destination
Immediate data + Destination ⇒ Destination
Source + Destination + X ⇒ Destination
Source • Destination ⇒ Destination
Data • Destination ⇒ Destination
Source • CCR ⇒ CCR
Source • SR ⇒ SR
X/C
0
X/C
label
Dn, <ea>
# <data>, <ea>
Dn, <ea>
# <data>, <ea>
none
8, 16, 32
8, 32
8, 32
8, 32
8, 32
none
# <data>
none
label
Dn, <ea>
# <data>, <ea>
label
Dn, <ea>
# <data>, <ea>
<ea>, Dn
<ea>, Rn
8, 16, 32
8, 32
8, 32
8, 16, 32
8, 32
8, 32
16, 32
8, 16, 32
Í
<ea>, Dn
<ea>, An
# <data>, <ea>
(An) +, (An) +
<ea>, Rn
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
If condition true, then PC + d ⇒ PC
bit number〉 of destination) ⇒ Z ⇒ bit of destinatio
( 〈 bit number〉 of destination)
0 ⇒ Zbit of destination
If background mode enabled, then enter background
mode, else format/vector ⇒ − (SSP);
PC ⇒ − (SSP); SR ⇒ − (SSP); (vector) ⇒ PC
If breakpoint cycle acknowledged, then execute
returned operation word, else trap as illegal instruction
PC + d ⇒ PC
( 〈 bit number〉 of destination) ⇒ Z;
1 ⇒ bit of destination
SP − 4 ⇒ SP; PC ⇒ (SP); PC + d ⇒ PC
( 〈 bit number〉 of destination) ⇒ Z
If Dn < 0 or Dn > (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
0 ⇒ Destination
(Destination − Source), CCR shows results
(Destination − Source), CCR shows results
(Destination − Data), CCR shows results
(Destination − Source), CCR shows results
Lower bound ≤ Rn ≤ Upper bound, CCR shows result
MC68332
MC68332TS/D
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