MC34932 Datasheet, PDF (8/24 Pages) Freescale Semiconductor, Inc – Dual 5.0 A H-Bridge

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 5.0 V ≤ V_PWR ≤ 28 V, -40 °C ≤ T_A ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25 °C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
TIMING CHARACTERISTICS
PWM Frequency⁽²⁰⁾
Maximum Switching Frequency During Current Limit Regulation⁽²¹⁾
Output ON Delay⁽²²⁾
V_PWR = 14 V
Output OFF Delay⁽²²⁾
V_PWR = 14 V
I_LIM Output Constant-OFF Time^{(23) (25)}
I_LIM Blanking Time^{(24) (25)}
Disable Delay Time⁽²⁶⁾
Output Rise and Fall Time⁽²⁷⁾
Short-circuit / Overtemperature Turn-OFF (Latch-OFF) Time^{(28), (29)}
Power-ON Delay Time⁽²⁹⁾
Output MOSFET Body Diode Reverse Recovery Time⁽²⁹⁾
Charge Pump Operating Frequency⁽²⁹⁾
f _PWM
–
f _MAX
–
t _DON
–
–
11
kHz
–
20
kHz
μs
–
18
t _DOFF
–
μs
–
12
t_A
15
20.5
32
μs
t_B
12
16.5
27
μs
t _DDISABLE
–
–
8.0
μs
t _F, t _R
1.5
3.0
8.0
μs
t _FAULT
–
–
8.0
μs
t _POD
–
1.0
5.0
ms
t_RR
75
100
150
ns
f_CP
–
7.0
–
MHz
Notes
20. The maximum PWM frequency should be limited to frequencies < 11 kHz in order to allow the internal high side driver circuitry time to
fully enhance the high side MOSFETs at a duty cycle range of 15 to 85%.
21. The internal current limit circuitry produces a constant-OFF-time Pulse Width Modulation of the output current. The output load’s
inductance, capacitance, and resistance characteristics affect the total switching period (OFF-time + ON-time), and thus the PWM
frequency during current limit.
22. * Output Delay is the time duration from 1.5 V on the IN1 or IN2 input signal to the 20% or 80% point (dependent on the transition direction)
of the OUT1 or OUT2 signal. If the output is transitioning HIGH-to-LOW, the delay is from 1.5 V on the input signal to the 80% point of
the output response signal. If the output is transitioning LOW-to-HIGH, the delay is from 1.5 V on the input signal to the 20% point of the
output response signal. See Figure 4, page 9.
23. The time during which the internal constant-OFF time PWM current regulation circuit has tri-stated the output bridge.
24. The time during which the current regulation threshold is ignored so the short-circuit detection threshold comparators may have time to
act.
25. Parameter guaranteed by characterization.
26. * Disable Delay Time measurement is defined in Figure 5, page 9.
27. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal with V_PWR = 14 V,
R_LOAD = 3.0 ohm. See Figure 6, page 9.
28. Load currents ramping up to the current regulation threshold become limited at the I_LIM value (see Figure 7). The short-circuit currents
possess a di/dt which ramps up to the I_SCH or I_SCL threshold during the I_LIM blanking time, registering as a short-circuit event detection
and causing the shutdown circuitry to force the output into an immediate tri-state latch-OFF (see Figure 8). Operation in Current Limit
mode may cause junction temperatures to rise. Junction temperatures above ~160 °C causes the output current limit threshold to “fold
back”, or decrease, until ~175 °C is reached, after which the t_LIM thermal latch-OFF occurs. Permissible operation within this fold back
region is limited to non-repetitive transient events of duration not to exceed 30 seconds (see Figure 9).
29. Parameter is Guaranteed By Design.
34932
8
Analog Integrated Circuit Device Data
Freescale Semiconductor