MC34932 Datasheet, PDF (4/24 Pages) Freescale Semiconductor, Inc – Dual 5.0 A H-Bridge

PIN CONNECTIONS
Table 1. 34932 Pin Definitions (continued)
Pin
Number
Pin
Pin Name _Function
Formal Name
Definition
15, 16, 39, PGNDB
40
Power
Ground
Power Ground
High-current power ground pins must be connected together physically as close
as possible and directly soldered down to a wide, thick, low resistance ground
plane on the PCB. PGNDB should be connected to PGNDA with a low-
impedance path.
17, 18
19, 26, 28,
36
20
OUT4
VPWRB
CCPB
Power
Output
H-Bridge Output 4
Power Input Positive Power
Supply
Analog
Output
Charge Pump
Capacitor
H-Bridge B Source of HS2 and drain of LS2.
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the PCB.
External reservoir capacitor connection for H-Bridge B internal charge pump;
connected to VPWRB. Allowable values are 30 to 100 nF. Note: This capacitor
is required for the proper performance of the device.
23
IN4
Logic Input
Input 4
Logic input control of OUT4.
24
IN3
Logic Input
Input 3
Logic input control of OUT3.
25
SFB
Logic
Status Flag B H-Bridge B open drain active LOW Status Flag output (requires an external pull-
Output -
(Active Low)
up resistor to V_DD. Maximum permissible load current < 0.5 mA. Maximum
Open Drain
V_SFLOW < 0.4 V at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
30
D3
Logic Input Disable Input 3 When D3 is logic HIGH, both OUT3 and OUT4 are tri-stated. Schmitt trigger
(Active High)
input with ~80 μA source so default condition = disabled.
31
FBB
Analog
Feedback B
H-Bridge B load current feedback output provides ground referenced 0.24% of
Output
the high side output current. (Tie to GND through a resistor if not used.)
32
37, 38
44, 45
47
EN/D4
OUT3
OUT2
CCPA
Logic Input
Power
Output
Power
Output
Analog
Output
Enable Input
H-Bridge Output 3
H-Bridge Output 2
Charge Pump
Capacitor
When EN/D4 is logic HIGH, H-Bridge B is operational. When EN/D4 is logic
LOW, the H-Bridge B outputs are tri-stated and H-Bridge B is placed in Sleep
Mode. (logic input with ~ 80μA sink so default condition = Sleep Mode.)
H-Bridge B Source of HS1 and drain of LS1.
H-Bridge A source of HS2 and drain of LS2.
External reservoir capacitor connection for H-Bridge A internal charge pump;
connected to VPWRA. Allowable values are 30 to 100 nF. Note: This capacitor
is required for the proper performance of the device.
50
IN2
Logic Input
Input 2
Logic input control of OUT2.
51
IN1
Logic Input
Input 1
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to
VPWRA, and when IN1 is logic LOW, OUT1 is set to PGNDA. (Schmitt trigger
Input with ~ 80 μA source so default condition = OUT1 HIGH.)
52
54
27
2, 6 - 8, 14,
21, 22, 29,
33 - 35, 41,
48, 49
EP
SFA
AGNDA
AGNDB
NC
EP
Logic
Output -
Open Drain
Analog
Ground
None
Thermal
Pad
Status Flag
(Active Low)
Analog Signal
Ground
No Connect
Exposed Pad
H-Bridge A open drain active LOW Status Flag output (requires an external pull-
up resistor to V_DD. Maximum permissible load current < 0.5 mA. Maximum
V_SFLOW< 0.4 V at 0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
The low-current analog signal ground must be connected to PGND via low-
impedance path (<10 mΩ, 0 Hz to 20 kHz).
These pins have no electrical connection or function.
Exposed TAB is also the main heatsinking path for the device and must be
connected to ground.
34932
4
Analog Integrated Circuit Device Data
Freescale Semiconductor