MC68332ACEH16 Datasheet, PDF (77/88 Pages) Freescale Semiconductor, Inc – 32-Bit Modular Microcontroller

Freescale Semiconductor, Inc.
D00
RR0
RR1
RR2
RECEIVE
RAM
RRD
RRE
D1E
RRF
WORD
D20
TR0
TR1
TR2
TRANSMIT
RAM
TRD
TRE
D3E
TRF
WORD
D40
CR0
CR1
CR2
COMMAND
RAM
CRD
CRE
D4F
CRF
BYTE
Figure 15 QSPI RAM
QSPI RAM MAP
Once the CPU has set up the queue of QSPI commands and enabled the QSPI, the QSPI can operate
independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating
that it is finished, and then either interrupts the CPU or waits for CPU intervention. It is possible to ex-
ecute a queue of commands repeatedly without CPU intervention.
RR[0:F] — Receive Data RAM
$YFFD00
Data received by the QSPI is stored in this segment. The CPU reads this segment to retrieve data from
the QSPI. Data stored in receive RAM is right-justified. Unused bits in a receive queue entry are set to
zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using
byte, word, or long-word addressing.
The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this infor-
mation to determine which locations in receive RAM contain valid data before reading them.
TR[0:F] — Transmit Data RAM
$YFFD20
Data that is to be transmitted by the QSPI is stored in this segment. The CPU usually writes one word
of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit data RAM in a right-justified format. The QSPI
cannot modify information in the transmit data RAM. The QSPI copies the information to its data serial-
izer for transmission. Information remains in transmit RAM until overwritten.
CR[0:F] — Command RAM
7
6
5
CONT
BITSE
DT
4
DSCK
3
PCS3
2
PCS2
$YFFD40
1
PCS1
0
PCS0*
—
—
—
—
—
—
—
—
CONT
BITSE
DT
DSCK
PCS3
PCS2
PCS1
PCS0*
COMMAND CONTROL
*The PCS0 bit represents the dual-function PCS0/SS.
PERIPHERAL CHIP SELECT
MC68332
MC68332TS/D
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MOTOROLA
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